A real-time high performance edge detector for computer vision applications
نویسندگان
چکیده
We present a high performance edge detection architecture for real-time image processing applications. The architecture is nely pipelined. The proposed ASIC is capable of producing one edge{pixel every clock cycle. At a clock rate of 10 MHz, the architecture can process 30 frames per second, where the size of each frame is 640 480 8{bit pixels. The ASIC was laid out and fabricated using Samsung's 0.8 m double{metal CMOS process.
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تاریخ انتشار 1997